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Su ZHENG (鄭溯)Postdoctoral Researcher
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Biography
I am a Postdoctoral Researcher in the Department of Electrical Engineering and Computer Science (EECS) at Massachusetts Institute of Technology (MIT), working with Prof. Duane Boning.
I received my Ph.D. degree from the Department of Computer Science and Engineering, the Chinese University of Hong Kong (CUHK),
under the supervision of Prof. Bei YU and Prof. Martin D.F. Wong since Fall 2022.
I also spent one year as a visiting scholar in Prof. Jason Cong’s lab at University of California, Los Angeles (UCLA), during 2024.09-2025.09.
Prior to that, I obtained my B.Eng. and M.S. degree from Fudan University under the supervision of Prof. Lingli Wang in 2015-2022.
My research interest is to solve critical problems in electronic design automation (EDA) with advanced artificial intelligence (AI) methods. Besides research, I love playing the piano and listening to classical music in my spare time.
Recent News
Feb/2026: Congratulation! Our work on ASIC HLS has been accepted by TCAD!
Feb/2026: Congratulation! Our work DR. OPC has been accepted by DAC 2026!
Apr/2025: Congratulation! Our work on pattern database has been accepted by TCAD!
Feb/2025: Congratulation! Our work on curvilinear OPC has been accepted by DAC 2025!
Jan/2025: Congratulation! Our work on congestion prediction has been accepted by TCAD!
Sep/2024: Congratulation! Our work on Neural ODE has been accepted by NeurIPS 2024!
Feb/2024: Congratulation! Our work on LLM for EDA has been accepted by TCAD!
Research Interests
AI for Electronic Design Automation
Computational Lithography
High-Level Synthesis
Physical Design
FPGA, CGRA, Approximate Computing
Journal Papers
[J20] Su Zheng, Zijian Ding, Chengyue Wang, Bei Yu, Martin Wong, Yizhou Sun, Jason Cong, “Enhancing ASIC HLS Design Optimization via Knowledge Transfer from FPGA HLS Models”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2026.
[J19] Su Zheng, Zhengqi Gao, Fan-Keng Sun, Duane S. Boning, Ron Rohrer, Bei Yu, Martin D.F. Wong, “KirchhoffNet: End-to-End Analog Circuit Acceleration for ODE-Based Neural Networks”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2026.
[J18] Su Zheng, Wenqian Zhao, Shuyuan Sun, Fan Yang, Bei Yu, Martin D.F. Wong, “Streamlining Computational Lithography with Efficient Pattern Database”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 44, no. 11, pp. 4263–4275, 2025.
[J17] Su Zheng, Bei Yu, Martin Wong, “Accelet: Hardware-software Co-design of Chiplet-based DNN Accelerators”, ACM Transactions on Design Automation of Electronic Systems (TODAES), 2026.
[J16] Su Zheng, Hao Geng, Chen Bai, Bei Yu, Martin Wong, “Boosting VLSI Design Flow Parameter Tuning with Random Embedding and Multi-objective Trust-region Bayesian Optimization”, ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 28, no. 05, pp. 1–23, 2023.
[J15] Peng Xu, Rong Sun, Su Zheng, Song Chen, Qi Xu, Bei Yu, “DaVinci: Performance-Driven Analog Routing via Multi-modality Guidance Prediction”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2026.
[J14] Xinyun Zhang, Yuyang Chen, Yiwen Wu, Su Zheng, Ran Chen, Min Li, Hao Geng, Binwu Zhu, Mingxuan Yuan, Bei Yu, “From Contrastive to Generative Alignment: Large-Scale Hierarchical Multi-Modal Pre-training for Hotspot Detection”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2026.
[J13] Shuo Yin, Ziyang Yu, Wenqian Zhao, Lancheng Zou, Jiahao Xu, Su Zheng, Yuzhe Ma, Tsung-Yi Ho, Bei Yu, “FuILT-S: Full Chip ILT With Unified Boundary Healing and SRAF Co-Optimization”, ACM Transactions on Design Automation of Electronic Systems (TODAES), 2026.
[J12] Donger Luo, Qi Sun, Peng Xu, Su Zheng, Qi Xu, Tinghuan Chen, Bei Yu, Hao Geng, “Attention-Based EDA Tool Parameter Explorer: From Hybrid Parameters to Multi-QoR Metrics”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 45, no. 02, pp. 691–704, 2025.
[J11] Peng Xu, Su Zheng, Yuyang Ye, Chen Bai, Siyuan Xu, Hao Geng, Tsung-Yi Ho, Bei Yu, “RankTuner: When Design Tool Parameter Tuning Meets Preference Bayesian Optimization”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2025.
[J10] Yuyang Chen, Qi Sun, Su Zheng, Xinyun Zhang, Bei Yu, Hao Geng, “HyDAS: Hybrid Domain Deformed Attention for Selective Hotspot Detection”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2025.
[J9] Peng Xu, Su Zheng, Mingzi Wang, Ziyang Yu, Shixin Chen, Tinghuan Chen, Keren Zhu, Tsung-Yi Ho, Bei Yu, “Rank-DSE: Neural Pareto Comparator of Microarchitecture Design Space Exploration”, ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 30, no. 05, pp. 71:1–71:24, 2025.
[J8] Binwu Zhu, Su Zheng, Yuzhe Ma, Bei Yu, Martin Wong, “Bridging Hotspot Detection and Mask Optimization via Domain-Crossing Masked Layout Modeling”, ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 30, no. 04, pp. 54:1–54:20, 2025.
[J7] Lancheng Zou, Su Zheng, Peng Xu, Siting Liu, Bei Yu, Martin D.F. Wong, “Lay-Net: Grafting Netlist Knowledge on Layout-Based Congestion Prediction”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 44, no. 07, pp. 2627–2640, 2025.
[J6] Ziyang Yu, Su Zheng, Wenqian Zhao, Shuo Yin, Xiaoxiao Liang, Guojin Chen, Yuzhe Ma, Bei Yu, Martin D.F. Wong, “RuleLearner: OPC Rule Extraction from Inverse Lithography Technique Engine”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 44, no. 05, pp. 1915–1927, 2025.
[J5] Haoyuan Wu, Zhuolun He, Xinyun Zhang, Xufeng Yao, Su Zheng, Haisheng Zheng, Bei Yu, “ChatEDA: A Large Language Model Powered Autonomous Agent for EDA”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 43, no. 10, pp. 3184–3197, 2024.
[J4] Shixin Chen, Shanyi Li, Zhen Zhuang, Su Zheng, Zheng Liang, Tsung-Yi Ho, Bei Yu, Alberto L. Sangiovanni-Vincentelli, “Floorplet: Performance-aware Floorplan Framework for Chiplet Integration”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 43, no. 06, pp. 1638–1649, 2024.
[J3] Binwu Zhu, Su Zheng, Ziyang Yu, Guojin Chen, Yuzhe Ma, Fan Yang, Bei Yu, Martin Wong, “L2O-ILT: Learning to Optimize Inverse Lithography Techniques”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 43, no. 03, pp. 944–955, 2024.
[J2] Sichao Chen, Chang Cai, Su Zheng, Jiangnan Li, Guowei Zhu, Jingyuan Li, Yazhou Yan, Yuan Dai, Wenbo Yin, Lingli Wang, “HierCGRA: A Novel Framework for Large-Scale CGRA with Hierarchical Modeling and Automated Design Space Exploration”, ACM Transactions on Reconfigurable Technology and Systems (TRETS), 2024
[J1] Zhen Li, Su Zheng, Jide Zhang, Yao Lu, Jingbo Gao, Jun Tao, Lingli Wang, “Adaptable Approximate Multiplier Design Based on Input Distribution and Polarity,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 30, no. 12, pp. 1813-1826, Dec. 2022.
Conference Papers
[C23] Su Zheng, Xinyun Zhang, Bei Yu, Martin Wong, “DR. OPC: Differentiable Rasterization for Advanced Optical Proximity Correction”, ACM/IEEE Design Automation Conference (DAC), Long Beach, Jul. 26–29, 2026.
[C22] Su Zheng, Xiaoxiao Liang, Ziyang Yu, Yuzhe Ma, Bei Yu and Martin Wong, “Curvilinear Optical Proximity Correction via Cardinal Spline”, ACM/IEEE Design Automation Conference (DAC), San Francisco, Jun. 22–25, 2025.
[C21] Su Zheng, Yuzhe Ma, Bei Yu, Martin Wong, “EMOGen: Enhancing Mask Optimization via Pattern Generation”, ACM/IEEE Design Automation Conference (DAC), San Francisco, Jun. 23–27, 2024.
[C20] Su Zheng, Lancheng Zou, Siting Liu, Yibo Lin, Bei Yu, Martin Wong, “Mitigating Distribution Shift for Congestion Optimization in Global Placement”, ACM/IEEE Design Automation Conference (DAC), San Francisco, Jul. 09–13, 2023.
[C19] Su Zheng, Zhengqi Gao, Fan-Keng Sun, Duane S. Boning, Bei Yu, Martin D. Wong, “Improving Neural ODE Training with Temporal Adaptive Batch Normalization”, Neural Information Processing Systems (NeurIPS), Vancouver, Dec. 09–15, 2024.
[C18] Su Zheng, Haoyu Yang, Binwu Zhu, Bei Yu, Martin D.F. Wong, “LithoBench: Benchmarking AI Computational Lithography for Semiconductor Manufacturing”, Neural Information Processing Systems (NeurIPS), New Orleans, Dec. 10–16, 2023.
[C17] Su Zheng, Ziyang Yu, Bei Yu, Martin Wong, “Scalable Second-Order Optimizer for Full-Chip Inverse Lithography Techniques”, IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), Verona, Italy, Apr. 20–22, 2026.
[C16] Su Zheng, Lancheng Zou, Peng XU, Siting Liu, Bei Yu, Martin Wong, “Lay-Net: Grafting Netlist Knowledge on Layout-Based Congestion Prediction”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Francisco, Oct. 29–Nov. 02, 2023.
[C15] Su Zheng, Gang Xiao, Ge Yan, Meng Dong, Hong Chen, Yuzhe Ma, Bei Yu, Martin Wong, “Model-based OPC Extension in OpenILT”, International Symposium of EDA (ISEDA), May 10–13, 2024.
[C14] Su Zheng, Bei Yu, Martin Wong, “OpenILT: An Open Source Inverse Lithography Technique Framework”, IEEE International Conference on ASIC (ASICON), Nanjing, Oct. 24–27, 2023. (Invited Paper)
[C13] Su Zheng, Jiadong Qian, Hao Zhou, Lingli Wang, “GRAEBO: FPGA General Routing Architecture Exploration via Bayesian Optimization,” The International Conference on Field-Programmable Logic and Applications (FPL), 2022.
[C12] Su Zheng, Zhen Li, Yao Lu, Jingbo Gao, Jide Zhang and Lingli Wang, “HEAM: High-Efficiency Approximate Multiplier optimization for Deep Neural Networks,” 2022 IEEE International Symposium on Circuits and Systems (ISCAS), 2022. (code)
[C11] Su Zheng, Kaisen Zhang, Yaoguang Tian, Wenbo Yin, Lingli Wang and Xuegong Zhou, “FastCGRA: A Modeling, Evaluation, and Exploration Platform for Large-Scale Coarse-Grained Reconfigurable Arrays,” International Conference on Field-Programmable Technology (ICFPT), 2021.
[C10] Su Zheng, Jialin Chen and Lingli Wang, “Targeted Black-Box Adversarial Attack Method for Image Classification Models,” 2019 International Joint Conference on Neural Networks (IJCNN), 2019. (code)
[C9] Ziyang Yu, Shuo Yin, Su Zheng, Xiaoxiao Liang, Yuzhe Ma, Bei Yu, “Coordinated Clip-Wise Gradient Scheduling for Full-Chip ILT via Policy Learning”, ACM/IEEE Design Automation Conference (DAC), Long Beach, Jul. 26–29, 2026.
[C8] Ziyang Yu, Peng Xu, Su Zheng, Siyuan Xu, Hao Geng, Bei Yu, Martin D.F. Wong, “CausalTuner: Will Causality Help High-Dimensional EDA Tool Parameter Tuning”, IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Hong Kong, Jan. 19–22, 2026.
[C7] Shuo Yin, Su Zheng, Ziyang Yu, Bei Yu, “TorchLitho 2.0: Ultrafast Differentiable Lithography Simulation Engine”, IEEE International Conference on ASIC (ASICON), Kunming, Oct. 21–24, 2025. (Invited Paper)
[C6] Zixiao Wang, Jieya Zhou, Su Zheng, Shuo Yin, Kaichao Liang, Shoubo Hu, Xiao Chen, Bei Yu, “TorchResist: Open-source differentiable resist simulator”, SPIE Advanced Lithography + Patterning, San Jose, Feb. 23–27, 2025.
[C5] Peng Xu, Su Zheng, Yuyang Ye, Chen Bai, Siyuan Xu, Hao Geng, Tsung-Yi Ho, Bei Yu, “RankTuner: When Design Tool Parameter Tuning Meets Preference Bayesian Optimization”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), New Jersey, Oct. 27–31, 2024.
[C4] Xinyun Zhang, Su Zheng, Guojin Chen, Binwu Zhu, Hong Xu, Bei Yu, “Fracturing-aware Curvilinear ILT via Circular E-beam Mask Writer”, ACM/IEEE Design Automation Conference (DAC), San Francisco, Jun. 23–27, 2024.
[C3] Shixin Chen, Su Zheng, Chen Bai, Wenqian Zhao, Shuo Yin, Yang Bai, Bei Yu, “SoC-Tuner: An Importance-guided Exploration Framework for DNN-targeting SoC Design”, IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), South Korea, Jan. 22–25, 2024.
[C2] Zhuolun He, Haoyuan Wu, Xinyun Zhang, Xufeng Yao, Su Zheng, Haisheng Zheng and Bei Yu, “ChatEDA: A Large Language Model Powered Autonomous Agent for EDA”, ACM/IEEE Workshop on Machine Learning for CAD (MLCAD), Utah, Sep. 11-13, 2023.
[C1] Yao Lu, Jide Zhang, Su Zheng, Zhen Li, Lingli Wang, “Low Error-Rate Approximate Multiplier Design for DNNs with Hardware-Driven Co-Optimization,” 2022 IEEE International Symposium on Circuits and Systems (ISCAS), 2022.
Education
Ph.D., Department of Computer Science and Engineering, The Chinese University of Hong Kong (CUHK), Aug/2022 - Now
M.S., State Key Laboratory of ASIC & System, Fudan University (FDU), Sep/2019 - Jun/2022
B.Eng. (Elite Engineering Honor Degree, Rank 1st), School of Microelectronics, Fudan University (FDU), Sep/2015 - Jun/2019
Projects
LithoBench, an open-source dataset for AI-driven computation lithography.
OpenILT, an open-source inverse lithography technology platform.
TorchResist, an open-source litho-resist simulator, lead by Zixiao Wang.
FastCGRA, a platform for large-scale CGRA, 40k+ lines of C++ code, also named HierCGRA. Thanks for Chang's efforts!
SimpleCGRA, a simple and efficient CGRA platform, implemented with Python and LLVM.
ApproxFlow, an approximate multiplier design and evaluation platform for deep learning, 10k+ lines of C++ code.
Black-box-attack, a targeted black-box adversarial attack method for image classification models.
Selected Awards
| Third Place (4/25), | EDAthon 2023 | 2023 |
| Full Postgraduate Studentship, | The Chinese University of Hong Kong, | 2022-2026 |
| First Class Scholarship, | Fudan University, | 2015-2018 |
Skills
Languages: C/C++, Python, Verilog, Perl, Haskell, Matlab, R, Java
Tools : PyTorch, Tensorflow, Caffe, Vivado, LaTeX
Hobbies : Piano, Classical Music