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Su ZHENG (鄭溯)Ph.D. Student
Department of Computer Science and Engineering
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Biography
I am a third-year Ph.D. Student at the Department of Computer Science and Engineering, the Chinese University of Hong Kong (CUHK),
under the supervision of Prof. Bei YU and Prof. Martin D.F. Wong since Fall 2022. Prior to that, I obtained my B.Eng. and M.S. degree from Fudan University under the supervision of Prof. Lingli Wang in 2015-2022.
My research interest is to solve critical problems in electronic design automation (EDA) with advanced artificial intelligence (AI) methods. Besides research, I love playing the piano and listening to classical music in my spare time.
Recent News
Oct/2024: Congratulation! Our work on OPC has been accepted by TCAD!
Sep/2024: Congratulation! Our work on Neural ODE has been accepted by NeurIPS!
Jun/2024: Congratulation! Our work on ranking-based design space exploration has been accepted by ICCAD!
Feb/2024: Congratulation! Our work on LLM for EDA has been accepted by TCAD!
Feb/2024: Congratulation! Our two works on mask optimization and pattern generation has been accepted by DAC!
Research Interest
AI in Electronic Design Automation
Optical Proximity Correction
VLSI Placement
Design Space Exploration
Coarse Grained Reconfigurable Arrays
Approximate Computing
Publication
[J7] Z. Yu, S. Zheng, W. Zhao, S. Yin, X. Liang, G. Chen, Y. Ma, B. Yu, M. D.F. Wong, “RuleLearner: OPC Rule Extraction from Inverse Lithography Technique Engine”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD).
[C15] S. Zheng, Z. Gao, F-K Sun, D. S. Boning, B. Yu, M. D.F. Wong, “Improving Neural ODE Training with Temporal Adaptive Batch Normalization”, Neural Information Processing Systems (NeurIPS), 2024.
[C14] P. Xu, S. Zheng, Y. Ye, C. Bai, S. Xu, H. Geng, T. Ho, B. Yu, “RankTuner: When Design Tool Parameter Tuning Meets Preference Bayesian Optimization”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), New Jersey, Oct. 27–31, 2024.
[J6] S. Chen, C. Cai, S. Zheng, J. Li, G. Zhu, J. Li, Y. Yan, Y. Dai, W. Yin, L. Wang, “HierCGRA: A Novel Framework for Large-Scale CGRA with Hierarchical Modeling and Automated Design Space Exploration”, ACM Transactions on Reconfigurable Technology and Systems (TRETS), 2024
[J5] H. Wu, Z. He, X. Zhang, X. Yao, S. Zheng, H. Zheng, B. Yu, “ChatEDA: A Large Language Model Powered Autonomous Agent for EDA”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2024.
[C13] S. Zheng, Y. Ma, B. Yu, M. Wong, “EMOGen: Enhancing Mask Optimization via Pattern Generation”, ACM/IEEE Design Automation Conference (DAC), San Francisco, Jun. 23–27, 2024.
[C12] X. Zhang, S. Zheng, G. Chen, B. Zhu, H. Xu, B. Yu, “Fracturing-aware Curvilinear ILT via Circular E-beam Mask Writer”, ACM/IEEE Design Automation Conference (DAC), San Francisco, Jun. 23–27, 2024.
[J4] S. Chen, S. Li, Z. Zhuang, S. Zheng, Z. Liang, T. Ho, B. Yu, A. L. Sangiovanni-Vincentelli, “Floorplet: Performance-aware Floorplan Framework for Chiplet Integration”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD).
[C11] Z. He, H. Wu, X. Zhang, X. Yao, S. Zheng, H. Zheng and B. Yu, “ChatEDA: A Large Language Model Powered Autonomous Agent for EDA”, ACM/IEEE Workshop on Machine Learning for CAD (MLCAD), 2023.
[C10] S. Zheng, H. Yang, B. Zhu, B. Yu, M. D.F. Wong, “LithoBench: Benchmarking AI Computational Lithography for Semiconductor Manufacturing”, Neural Information Processing Systems (NeurIPS) Datasets and Benchmarks Track, 2023.
[J3] B. Zhu, S. Zheng, Z. Yu, G. Chen, Y. Ma, F. Yang, B. Yu, M. D.F. Wong, “L2O-ILT: Learning to Optimize Inverse Lithography Techniques”, accepted by IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD).
[C9] S. Chen, S. Zheng, C. Bai, W. Zhao, S. Yin, Y. Bai, B. Yu, “SoC-Tuner: An Importance-guided Exploration Framework for DNN-targeting SoC Design”, IEEE/ACM Asian and South Pacific Design Automation Conference (ASP-DAC), 2023.
[C8] S. Zheng, B. Yu, M. D.F. Wong, “OpenILT: An Open Source Inverse Lithography Technique Framework”, International Conference on ASIC (ASICON), 2023 (Invited Paper).
[C7] S. Zheng, L. Zou, P.Xu, S. Liu, B. Yu, M. D.F. Wong, “Lay-Net: Grafting Netlist Knowledge on Layout-Based Congestion Prediction”, International Conference on Computer-Aided Design (ICCAD), 2023.
[J2] S. Zheng, H. Geng, C. Bai, B. Yu, and M. Wong, Boosting vlsi design flow parameter tuning with random embedding and multi-objective trust-region bayesian optimization. ACM Transactions on Design Automation of Electronic Systems (TODAES), 2023.
[C6] S. Zheng, L. Zou, S. Liu, Y. Lin, B. Yu, M. D.F. Wong, “Mitigating Distribution Shift for Congestion Optimization in Global Placement”, Design Automation Conference (DAC), 2023.
[C4] S. Zheng, J. Qian, H. Zhou, L. Wang, “GRAEBO: FPGA General Routing Architecture Exploration via Bayesian Optimization,” The International Conference on Field-Programmable Logic and Applications (FPL), 2022.
[J1] Z. Li, S. Zheng, J. Zhang, Y. Lu, J. Gao, J. Tao, L. Wang, “Adaptable Approximate Multiplier Design Based on Input Distribution and Polarity,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 30, no. 12, pp. 1813-1826, Dec. 2022.
[C4] Y. Lu, J. Zhang, S. Zheng, Z. Li, L. Wang, “Low Error-Rate Approximate Multiplier Design for DNNs with Hardware-Driven Co-Optimization,” 2022 IEEE International Symposium on Circuits and Systems (ISCAS), 2022.
[C3] S. Zheng, Z. Li, Y. Lu, J. Gao, J. Zhang and L. Wang, “HEAM: High-Efficiency Approximate Multiplier optimization for Deep Neural Networks,” 2022 IEEE International Symposium on Circuits and Systems (ISCAS), 2022. (code)
[C2] S. Zheng, K. Zhang, Y. Tian, W. Yin, L. Wang and X. Zhou, “FastCGRA: A Modeling, Evaluation, and Exploration Platform for Large-Scale Coarse-Grained Reconfigurable Arrays,” International Conference on Field-Programmable Technology (ICFPT), 2021.
[C1] S. Zheng, J. Chen and L. Wang, “Targeted Black-Box Adversarial Attack Method for Image Classification Models,” 2019 International Joint Conference on Neural Networks (IJCNN), 2019. (code)
Education
Ph.D., Department of Computer Science and Engineering, The Chinese University of Hong Kong (CUHK), Aug/2022 - Now
M.S., State Key Laboratory of ASIC & System, Fudan University (FDU), Sep/2019 - Jun/2022
B.Eng. (Elite Engineering Honor Degree, Rank 1st), School of Microelectronics, Fudan University (FDU), Sep/2015 - Jun/2019
Projects
OpenILT, an open-source inverse lithography technology platform.
FastCGRA, a platform for large-scale CGRA, 40k+ lines of C++ code, also named HierCGRA. Thanks for Chang's efforts!
SimpleCGRA, a simple and efficient CGRA platform, implemented with Python and LLVM.
ApproxFlow, an approximate multiplier design and evaluation platform for deep learning, 10k+ lines of C++ code.
Black-box-attack, a targeted black-box adversarial attack method for image classification models.
Selected Awards
| Third Place (4/25), | EDAthon 2023 | 2023 |
| Full Postgraduate Studentship, | The Chinese University of Hong Kong, | 2022-2026 |
| First Class Scholarship, | Fudan University, | 2015-2018 |
Skills
Languages: C/C++, Python, Verilog, Perl, Haskell, Matlab, R, Java
Tools : PyTorch, Tensorflow, Caffe, Vivado, LaTeX
Hobbies : Piano, Classical Music